In the voltage doubler circuit shown in the figure, the switch ‘S

In the voltage doubler circuit shown in the figure, the switch ‘S
| In the voltage doubler circuit shown in the figure, the switch ‘S’ is closed at t = 0. Assuming diodes D1 and D2 to be ideal, load resistance to be infinite and initial capacitor voltages to be zero. The steady state voltage across capacitor C1 and C2 will be

A. Vc1 = 10 V, VC2 = 5 V

B. Vc1 = 10 V, VC2 = –5 V

C. Vc1 = 5 V, VC2 = 10 V

D. Vc1 = 5 V, VC2 = –10 V

Please scroll down to see the correct answer and solution guide.

Right Answer is: D

SOLUTION

The given circuit is

Step 1 : We have the input waveform, vi = 5 sin wt. So, we draw, the waveform as

Step 2 : For half part of the circuit. When positive half cycle of input is applied, diode D1 is ON and D2 is OFF. So, capacitor C1 will charge upto +5 Volt

VC1 = +5 Volt

This is a clamper circuit, So, output of the circuit is

In this clamper, diode is in downward position. So, it is negative clamper.

Step 3 : Second part of the circuit is peak detector as shown below.

So, it allows only peaks at the output. Thus, from the results obtained in the above step, the output voltage is

VC2 = –10 Volt

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