The output (Y) of the circuit shown in the figure is
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The output (Y) of the circuit shown in the figure is
A. A̅ + B̅ + C
B. A + B̅ ⋅ C̅ + A ⋅ C̅
C. A̅ + B + C̅
D. A ⋅ B ⋅ C̅
Please scroll down to see the correct answer and solution guide.
Right Answer is: A
SOLUTION
Concept:
- The given circuit contains both NMOS and PMOS. So it is a CMOS implementation.
- For CMOS implementation if NMOS transistors are in series then PMOS transistors corresponding to their NMOS counterparts will be in parallel.
- Similarly, if NMOS transistors are in parallel then PMOS transistors corresponding to their NMOS counterparts will be in series.
- The output will be the negate of the function implemented by the NMOS transistors.
According to De morgan's theorem:
\(\overline {{A_1}.{A_2} \ldots \ldots {A_n}} = \overline {{A_1}} + \overline {{A_2}} + \ldots \overline {{A_n}} \)
Calculation:
In the given circuit, signals A, B, and C̅ are in series for NMOS implementation. ∴ The output will be:
\(\left( Y \right) = \overline {A.B.\bar C} = \bar A + \bar B + C\)