Which of the following has the highest noise margin

SOLUTION

• In a digital circuit, the Noise Margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.
• For Ex: a Digital circuit might be designed to swing between 0 and 1.2 Volts, with anything below 0.2 V considered as a ‘0’ and anything above 1 Volt is considered a ‘1’. Then the noise margin for a ‘0’ would be the amount that a signal is below 0.2 Volts, and a noise margin for 1 would be the amount by which a signal exceeds 1 Volt.
• In this case noise margins are measured as an absolute voltage, not as a ratio.
• This is schematically explained with the help of the following diagram:

• CMOS has the largest Noise Margin and ECL is having Poor Noise Margin.
• TTL outputs are typically restricted to narrower limits, between 0 V and 0.4 V for a “LOW” and between 2.4 V and Vcc for a “HIGH”, providing at least 0.4 V of noise immunity.
• Noise Margins for CMOS chips are usually much greater than those of TTL because the VOH(min) is closer to the power supply Voltage and VOL(max) is closer to 0.